High-speed data-communications systems typically incorporate multiple robust (gigabit-rate) serializer/deserializer (SerDes) chips that can send and receive parallel data over a serial link. Jitter is one of the most important issues in the design and operation of high-speed serial links. Although SerDes devices implement a purely digital function—serial data communications—they behave in an analog-like fashion, especially in the low-voltage differential signaling used at 10-Gbits/s speeds. And SerDes receivers and transmitters operate asynchronously: receiver and transmitter system clocks must operate within tolerances specified by the communications standard to which they conform, but they are not locked.
Synchronism across multiple High Speed SerDes (HSS) cores, requires clock signal gating function methods and circuitry. Clock gating in many applications is a necessity, and is typically accomplished by the use of a selector circuit or other switching devices inserted in the clock path, to switch between a “static” differential clock OFF condition and the desired clock. However problems arise through inserting an additional stage in the clock path, which degrades clock path performance and results in lower total system integrity while contributing additional jitter to the clock path.
What is needed is a clock gating method and system for synchronism across multiple High Speed SerDes (HSS) cores of very high frequency clocks that does not contribute to clock path jitter.